## Tuesday, December 25, 2007

### [TECH] Hanging simulation..

I came across a interesting problem in which the entire simulation was hanging just because of an extra non-sensitive always block , in the verilog code the statement "always dummy_reg = in;" was causing both VCS and NC-VERILOG hang. Theoretically speaking irrespective of what I do in my design the simulation should stop after 500 steps because I have a "#500 $finish" in the initial block of the module "TestHangMux", although I got around this problem by removing the "dummy_reg" totally in the multiplexer, but I still don't understand why the simulation was hanging irrespective of the "#500$finish" statement, is it because we have multiple non-sensitive "always" statement? the LRM(Language Reference Manual) says that all the "always" blocks execute in parallel just like parallel processors in that that the statement "#500 $finish" should have executed in parallel and stop the simulation but why it hangs?  =================================== module HangMux(in,sel,out); input [1:0]in; input sel; output out; reg [1:0]dummy_reg; reg out; always @(sel) begin case(sel) 0: out = dummy_reg[0]; 1: out = dummy_reg[1]; endcase end always dummy_reg = in; endmodule module TestHangMux(out_net); output out_net; wire out_net; reg [1:0]in_reg; reg sel; initial begin in_reg = 2'b01; sel = 0; #500$finish;
end

always begin
#10 sel = ~sel;
end

HangMux hang_me (in_reg,sel,out_net);
endmodule
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