Saturday, November 10, 2007

[TECH] Design of my first chip (A sequence Aligner O(n) space implementation)

Designing hardware is totally different from writing software, writing verilog code is totally different from writing software 'C' programs, often a software engineer tries to solve the problems using loops,arrays etc.. unfortunately implementing the same algorithm in hardware is totally different. I had my experience in designing a chip (verilog code) for finding edit distance between two strings this has a well known O(n^2) dynamic programming based algorithm. Now the trick is how do you create a hardware which realizes the two for loops in the O(n^2) algorithm, after quite a bit of thinking I came up with a solution which involves just SHIFTERS,MULTIPLEXERS and ADDERS. I'm not aware of any such hardware implementation of edit distance algorithm till now...I'm tempted to share my design diagram on the blog but I cannot do it until it gets published some where....

My design flow is as follows (verilog)->vcs; (libs+verilog)->Design Compiler; and I will use cadence virtuso (ICFB) for my placement and routing and also extraction; Will use HSPICE/Nanosim and spectre for postlayout simulation.

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