[TECH] why is ((unsigned long)a_ptr+(unsigned long)b_int) not equals (a_ptr+(unsigned long)b_int)

I was looking at some code today on SGI super computer, and wanted to make sure that there are no 32-64 bit problems in the code since SGI was super computer. I found the following thing to be interesting

<---------------------->
((unsigned long)a_ptr+(unsigned long)b_int)!=
          (a_ptr+(unsigned long)b_int)
<---------------------->

That is if I cast both the operands of binary + to (unsigned long) the value I get from that addition is different from if I cast just one operand of binary + to (unsigned long), whats the compiler doing here? since if both the operands to binary + are unsigned long and the value(no.of bits) could be larger than sizeof(unsigned long) is it the reason why I get different values here?, I couldn't find this in FAQ.

[TECH] Verilog incompatabilities between 'ncverilog' and 'vcs'

Thanksgiving vacation may be fun for some but its really not fun if your IT department is taking a break, our Synopsys License server has been down for last few days all my emails are vain no one responds. I used 'vcs' to compile all my verilog code all these days, now I'm helpless.....how can we solve this problem.
I want to get some synthesis metrics for the Sequence Alignment design, although Synopsys License server is down looks like the Cadence License server is up :). Thats good news but whats equivalent to 'vcs' in Cadence....'NCVERILOG' I found 'ncverilog' and try to compile all my design modules now the in-compatibility, NC-Verilog don't like to see any thing in the module description until all the port list is filled up,but vcs scans the code of the entire declaration list before checking if the port list is filled up (I guess thats the way it should be the algorithm should be very general). I like 'vcs' and not impressed by 'NC-Verilog' but unfortunately I have to live with it for few more days, by porting my verilog code...sounds crazy I have ported code on machines different processors but the way these compilers are build is really crazy....

[TECH] Iso-spectral and Non-Isomorphic Graphs (PINGS)

Having the same spectrum for the adjacency matrix is a Necessary but not sufficient condition for Graph Isomorphism, our recent algorithmic result states a conjecture that every graph is characterized by its Family of Spectra, rather than Spectrum itself.

I have been doing some work on efficient algorithms for generating PINGS (Pair of Isospectral and Non-Isomorphic Graphs), I wrote a program which can search for PINGS in a very efficient manner, I found some interesting results there are no PINGS for n=2,3,4 for n=5 we have one PING (see the picture) it happens that its the only PING for n=5 it has a symmetric spectrum of {-2,0,0,2}. Also I found a very interesting result that there cannot be more than two INGS(Iso-Spectral and non-isomorphic graphs) which share the same spectrum so if INGS exists they exist as PINGS, I was curious if they exist something like XINGS X=P or T or ... but it happens its just P (only a pair). There are 5 PINGS for n=6 for n=7 there are 55 PINGS see the list at http://trinity.engr.uconn.edu/~vamsik/n.7.

[TECH] Design of my first chip (A sequence Aligner O(n) space implementation)

Designing hardware is totally different from writing software, writing verilog code is totally different from writing software 'C' programs, often a software engineer tries to solve the problems using loops,arrays etc.. unfortunately implementing the same algorithm in hardware is totally different. I had my experience in designing a chip (verilog code) for finding edit distance between two strings this has a well known O(n^2) dynamic programming based algorithm. Now the trick is how do you create a hardware which realizes the two for loops in the O(n^2) algorithm, after quite a bit of thinking I came up with a solution which involves just SHIFTERS,MULTIPLEXERS and ADDERS. I'm not aware of any such hardware implementation of edit distance algorithm till now...I'm tempted to share my design diagram on the blog but I cannot do it until it gets published some where....

My design flow is as follows (verilog)->vcs; (libs+verilog)->Design Compiler; and I will use cadence virtuso (ICFB) for my placement and routing and also extraction; Will use HSPICE/Nanosim and spectre for postlayout simulation.